1. Field of the Invention
The present invention relates to a latch circuit in a semiconductor integrated circuit.
2. Description of Related Art
High-energy radiation incident on-a semiconductor chip induces errors and malfunction of various circuits. For example, the incident radiation can cause a phenomenon that a data (bit) stored on a node of a memory element is flipped. Such a phenomenon of the bit flip is called an “SEU (Single Event Upset)”.
A memory element such as an SRAM, a latch circuit or the like whose tolerance to the SEU is enhanced is described in: U.S. Pat. No. 6,696,873; T. Calin, et al., “Upset Hardened Memory Design for Submicron CMOS Technology”, IEEE TRANSACTIONS ON NUCLEAR SCIENCE, Vol. 43, No. 6, pp. 2874-2878, December 1996; P. Hazucha, et al., “Measurements and analysis of SER tolerant latch in a 90 nm dual-Vt CMOS process”, IEEE 2003 CUSTOM INTEGRATED CIRCUITS CONFERENCE, pp. 617-620, 2003; and M. J. Myjak, et al., “Enhanced Fault-Tolerant CMOS Memory Elements”, The 47th IEEE International Midwest Symposium on Circuits and Systems, pp. I-453-456, 2004. According to the techniques described in the above-mentioned documents, the memory element has four nodes and data are held at the four nodes. More specifically, data of the same value are held at two of the four nodes, while the inverted data are held at the other two nodes. That is, the data at the four nodes during a stable state are represented by [0, 1, 0, 1] or [1, 0, 1, 0]. In order to flip the data hold state, it is necessary to change the data at two or more nodes simultaneously. Even if the data at any one node is changed transiently for a short time period of the SEU, the data at the other three nodes are maintained. As a result, the data hold state of the four nodes returns back to the original stable state. In this manner, the SEU tolerance of the memory element is enhanced.
The inventor of the present application has recognized the following points. The radiation incident on a semiconductor chip can cause not only the bit flip in the memory element but also disturbance of an output signal level in a combination logic circuit. Such the radiation-induced disturbance of the signal level is called an “SET (Single Event Transient)”. The SET causes errors and malfunction of a semiconductor integrated circuit. For example, if the disturbance occurs in a clock signal supplied to a latch circuit, malfunction of the latch circuit can occur. In that case, the malfunction of the latch circuit results in a change (rewrite) of the stored data, even if no SEU occurs. A technique that can enhance tolerance of the latch circuit to the SET of the clock signal is desired.